1. Field of the Invention
The present invention relates to a content addressable memory or an associative memory comprising a number of word memories each for storing a bit pattern in units of words, and having such a function that retrieval data are inputted to the word memories and word memories, which have stored data having the same bit pattern as that of the retrieval data in its entirety or in a part specified, are retrieved.
2. Description of the Related Art
Recently, there has been proposed an associative memory provided with the retrieval function as mentioned above.
FIG. 6 is a circuit block diagram of the conventional associative memory by way of example.
Referring to FIG. 6, an associative memory 10 is provided with a number of word memories 11a, 11b, . . . , 11n each consisting of a 5-bit of serial memory cell. Further, the associative memory 10 comprises a retrieval register 12 which is adapted to receive and latch a word of retrieval data. A bit pattern of the retrieval data latched in the retrieval register 12 in its entirety or in a part specified is compared with a bit pattern of the portion corresponding to the bit pattern of the latched retrieval data with respect to data stored in each of the word memories 11a, 11b, . . . , 11n. As a result of the comparison, if there are found any of the word memories 11a, 11b, . . . , 11n of which the bit pattern matches with that of the retrieval data, a match signal given by a logic "1" (here 5.0 volt) will appear on the associated ones of match lines 14a, 14b, . . . , 14n which are provided in conjunction with the word memories 11a, 11b, . . . , 11n, respectively. On the other hand, a mismatch signal given by a logic "0" (here 0.0 volt) will appear on the remaining ones of the match lines 14a, 14b, . . . , 14n.
Assuming that the signals "0", "1", "0", "0", "1". . . , "0" appear on the flag lines 14a, 14b, . . . , 14n, respectively, these signals are applied to a priority encoder 15. The priority encoder 15 is so arranged to output an address signal AD corresponding to the match line given with a highest priority among the match lines (here, the match lines 14b and 14e) on which the match signal given by a logic "1" appears. Supposing that the priority is higher as alphabet of a suffix of the reference character becomes younger, in this case, the match line 14b is selected as the highest priority match line. Thus, the priority encoder 15 outputs an address signal AD corresponding to the highest priority match line 14b, which address signal AD is applied to an address decoder 16, in accordance with the necessity. The address decoder 16 decodes the received address signal AD and outputs an access signal (here a signal given by a logic "1") to the associated one (here a word line 17b) of word lines 17a, 17b, . . . , 17n which are provided in conjunction with the word memories 11a, 11b, . . . , 11n, respectively. Thus, data stored in the word memory 11b associated with the word line 17b on which the access signal appears is read out to an output data register 18.
As described above, according to the associative memory 10, the contents or data stored in a number of word memories 11a, 11b, . . . , 11n are retrieved using the retrieval data in its entirety or a part specified, so that an address of the word memory involved in the data match is generated, and thus it is possible to read out the whole data stored in the word memory.
FIG. 7 is a detailed circuit diagram of one of the word memories in the associative memory.
A word memory 11 comprises, for example, five memory cells 11-1, 11-2, . . . , and 11-5 each having the same structure. The memory cells 11-1, 11-2, . . . , and 11-5 are provided with first inverters 20-1, 20-2, . . . , and 20-5 and second inverters 21-1, 21-2, . . . , and 21-5, in pairs such that their outputs are connected to their inputs, respectively. Providing pairs of inverters 20-1 and 21-1; 20-2 and 21-2; . . . ; and 20-5 and 21-5 permits the memory cells 11-1, 11-2, . . . , and 11-5 to store one bit information expressed by logic "1" or logic "0", respectively.
In the memory cells 11-1, 11-2, . . . , and 11-5, the outputs of the first inverters 20-1, 20-2, . . . , and 20-5 are connected through N channel transistors 22-1, 22-2, . . . , and 22-5 to bit lines 23-1, 23-2, . . . , and 23-5, respectively. Gate electrodes of the transistors 22-1, 22-2, . . . , and 22-5 are connected to a word line 24. The outputs of the second inverters 21-1, 21-2, . . . , and 21-5 are connected through N channel transistors 25-1, 25-2, . . . , and 25-5 to bit bar lines 26-1, 26-2, . . . , and 26-5, respectively. Gate electrodes of the transistors 25-1, 25-2, . . . , and 25-5 are also connected to the word line 24. Further, in the memory cells 11-1, 11-2, . . . , and 11-5, there are provided pairs of N channel transistors 27-1 and 28-1; 27-2 and 28-2; . . . ; and 27-5 and 28-5, respectively, which are connected in series between the bit lines 23-1, 23-2, . . . , and 23-5 and the bit bar lines 26-1, 26-2, . . . , and 26-5, respectively. Gate electrodes of transistors 27-1, 27-2 . . . , and 27-5, as ones of these pairs of transistors 27-1 and 28-1; 27-2 and 28-2; . . . ; and 27-5 and 28-5, are connected to the outputs of the second inverters 21-1, 21-2, . . . , and 21-5, respectively; and gate electrodes of other transistors 28-1, 28-2, . . . , and 28-5 are connected to the outputs of the first inverters 20-1, 20-2, . . . , and 20-5, respectively.
Between a match line 14 and the ground GND, there are provided pairs of N channel transistors 29-1 and 35-1; 29-2 and 35-2; . . . ; and 29-5 and 35-5, respectively, which are each connected in series and correspond to the associated memory cell. Gate electrodes of the transistors 29-1, 29-2, . . . , and 29-5 at the side of the match line 14 are connected to points between the pairs of transistors 27-1 and 28-1; 27-2 and 28-2; . . . ; and 27-5 and 28-5, respectively; and gate electrodes of the transistors 35-1, 35-2, . . . , and 35-5 at the side of the ground GND are connected to a control line 30.
Connected to the match line 14, at the right hand in FIG. 7, is a sensing inverter 31 of which an output extends in the form of the match line 14 and is connected to the priority encoder 15 shown in FIG. 6.
Between an input of the inverter 31 and a power supply V.sub.DD, a pair P channel transistors 32 and 33 are disposed. Gate of the transistor 32 is connected to the control line 30. Gate of the transistor 33 is connected to the output of the inverter 31.
In the associative memory having the word memories as mentioned above in structure and its peripheral circuits, a match retrieval is conducted in a manner as set forth below.
Assuming that the memory cell 11-1 stores information of a logic "1", the output side of the first inverter 20-1 takes a state of a logic "1", and the output side of the second inverter 21-1 takes a state of a logic "0".
It is assumed that a retrieval for a logic "1" is performed for the above-mentioned memory cell 11-1. That is, the bit line 23-1 is enabled with a logic "1", and the bit bar line 26-1 is enabled with a logic "0". While the word line 24 is kept in a state of a logic "0". Since the logic levels "0" and "1" are applied to the gate electrodes of the transistors 27-1 and 28-1, respectively, the transistor 27-1 turns off and the transistor 28-1 turns on. Thus, the logic "0", which appears on the bit bar line 26-1, will be applied through the transistor 28-1 to the gate electrode of the transistor 29-1, so that the transistor 29-1 turns off.
To conduct a retrieval, first, the control line 30 is enabled with "0", so that a transistor 32 turns on whereby a match line 14 at the input side of the inverter 31 is precharged. Thereafter, the control line 30 is enabled with "1", so that a transistor 32 turns off to stop the precharge and the transistors 35-1, 35-2, . . . , and 35-5 turn on.
In case of the memory cell 11-1, however, as mentioned above, the transistor 29-1 is kept turning off. Accordingly, when all of the memory cells 11-1, 11-2, . . . , and 11-5 are in a state of the "match", the match line 14 is kept on precharge, so that the output of the inverter 31 becomes a logic "0".
Assuming that the memory cell 11-2 stores information of a logic "0", the output side of the first inverter 20-2 takes a state of a logic "0", and the output side of the second inverter 21-2 takes a state of a logic "1".
It is assumed that a retrieval for a logic "1" is also performed for the above-mentioned memory cell 11-2. That is, the bit line 23-2 is enabled with a logic "1", and the bit bar line 26-2 is enabled with a logic "0". Since the logic levels "1" and "0" are applied to the gate electrodes of the transistors 27-2 and 28-2, respectively, the transistor 27-2 turns on and the transistor 28-2 turns off. Thus, the logic "1", which appears on the bit line 23-2, will be applied through the transistor 27-2 to the gate electrode of the transistor 29-2, so that the transistor 29-2 turns on. That is, when the match line 14 is precharged and then the control line 30 is enabled with the logic "1", both the transistors 29-2 and 35-2 turn on, so that the electric charge, which has been precharged on the match line 14, is discharged through the transistors 29-2 and 35-2. Consequently, the input side of the inverter 31 becomes the logic "0", and the inverter 31 outputs a logic level "1" of signal.
In this manner, according to the word memory 11 shown in FIG. 7, when a stored bit pattern coincides with that of the entered retrieval data, the match line 14 is not discharged and thus the output of the inverter 31 becomes the logic "0". On the other hand, when mismatched, the match line 14 is discharged and thus the output of the inverter 31 becomes the logic "1". Incidentally, according to the word memory 11 shown in FIG. 7, the inverter 31 outputs a logic level "0" of signal when matched, and in this respect it is different from the explanation concerning FIG. 6. However, this problem will be solved simply by means of inverting the signals.
Now, through masking a part of the retrieval data latched in the retrieval data register 12, it is possible to conduct a retrieval for a match or mismatch for only the remaining bit pattern which is not masked. In this case, with respect to the masked bit, as shown concerning the memory cell 11-5, both the bit line 23-5 and the bit bar line 26-5 are enabled with the logic "0". In this case, while either the transistor 27-5 or the transistor 28-5 turns on in accordance with the fact that the memory cell 11-5 has stored logic "0" of information or logic "1" of information, the transistor 29-5 is kept turning off in any way, since both the bit line 23-5 and the bit bar line 26-5 are enabled with the logic "0". In other words, regarding the memory cell 11-5, it is considered that the stored information coincides with the retrieval information.
The constitution shown in FIG. 7 is of general in the conventional associative memory. In case of such a constitution, first, a number of match lines, which are provided for the associated word memories, respectively, are precharged and thereafter the match lines, which are involved in the mismatch and will occupy the majority of a number of match lines, are discharged whereby a match or mismatch is retrieved. Therefore, this involves such a problem that the precharge and discharge on the match lines consume very large electricity.
Further, the constitution shown in FIG. 7 will suffer from the following drawback.
FIG. 8 is a circuit diagram of a piece of memory cell as one element of the word memory shown in FIG. 7.
Here, for example, the first inverter 20 is representative of the first inverter 20-1, 20-2, . . . , and 20-5 shown in FIG. 7, and in this manner reference symbols are each depicted in a simple fashion so as to omit the numeral portion indicating the distinction among the memory cells.
Assuming that the memory cell shown in FIG. 8 stores information of a logic "0", the output side of the first inverter 20 takes a state of a logic "0", and the output side of the second inverter 21 takes a state of a logic "1". Now let us consider a case of the mismatch such that a logic "1" and a logic "0" are applied to the bit line 23 and the bit bar line 26, respectively.
In this condition, the transistor 27 turns on, so that the logic "1" appearing on the bit line 23 is applied to the gate electrode of the transistor 29. In a case where the potential of the bit line 23 is 5 V which is the same as the power supply voltage, about 3.6 V is applied to the gate electrode of the transistor 29 owing to the bias effect of the semiconductor substrate on which the associative memory is fabricated. Whereas, the match line 14 is precharged when the transistor 32 shown in FIG. 7 turns on. When the match line 14 is precharged, the potential on point P will rise up to, for example, about 7 V, owing to the presence of capacitance C.sub.p1 ; between the drain and gate electrodes of the transistor 29. In addition, the source electrode side (the point P side) of the transistor 27 becomes a higher potential than 5 V which is applied to the gate electrode thereof, and thus the transistor 27 turns off. While the transistor 28 is kept turning off since the logic "0" has been applied to the gate electrode thereof. Hence, a channel through which the electric charge on the point P passes will be broken, and thus the potential on the point P retains the above-mentioned about 7 V.
Recently, higher integration of an LSI advances, and also hereafter such a tendency will increasingly continue. However, if the point P becomes such a high potential that it exceeds the power supply voltage as mentioned above, this is in danger of destroying the transistors 27 and 28 when placed in a minuteness.